1. Field of the Invention
This invention relates generally to Analog to Digital Converters and, more specifically, to a High-speed Current Mode Analog to Digital Converter.
2. Description of Related Art
Generally, the architectures of the analog to digital converters (ADCs) are divided into two types: recursive and non-recursive. A recursive ADC includes some type of feedback circuit, one example of which is a successive-approximation type. A non-recursive ADC does not include a feedback circuit, such that the conversion is feed-forward only; examples of non-recursive ADCs include: flash, pipeline, folding and interpolating. The traditional successive-approximation type of ADC usually includes a digital-to-analog converter (DAC) and compares an input analog signal with an output of the DAC in order to confirm that the output of the DAC converter coincides with an input analog signal.
A benefit of the successive-approximation type of ADC is that the same circuitry is be used over and over again to determine each number of the digital bit of the analog to digital conversion. Thus, in general, it is more economical because smaller silicon die size can be achieved when a recursive type ADC. In contrast, higher speeds can be more easily achieved when non-recursive type of the ADC is used. Moreover, all of the conventional ADCs require certain stable generated voltages to serve as voltage references during the conversion between analog input signal and digital output. FIG. 1 depicts a conventional ADC.
FIG. 1 is a block diagram depicting a conventional analog to digital converter having successive approximation architecture 10. Analog VIN first enters the sample and hold device 12, where the signal is simply sampled and held in order to provide a buffer for the ADC. The delayed VIN next is applied to comparator 14, where it is compared to VDAC, which is the analog voltage (converted to from a digital signal) for a particular clock cycle. The digital comparison result is output by the comparator 14 to the successive approximation register (SAR) 16. The SAR adjusts the digital control signals in order to narrow the compared voltages, and outputs the adjusted digital control signals to a DAC 18. This adjusted digital signal is converted by the DAC 18 into VDAC, which is compared to VIN in the comparator 14. If we turn to FIG. 2, we can examine the steps involved in the operation of this conventional ADC.
FIG. 2 is a flowchart depicting the method of operation 20 of the ADC of FIG. 1. First (during the first clock period), the sample and hold circuit samples and holds the analog input signal (VIN) 100. Next, the sample and hold circuit outputs the analog voltage input signal to the comparator 102. The comparator compares VIN to VDAC and generates the digital result for Bit (n) 104. A high value (1) is obtained from the comparator if the value of VIN−VDAC is positive; a low value (0) is obtained from the comparator if the value is negative. The successive approximation register registers the Bit (N) result and updates the comparison voltage to a digital approximation of VREF/2, 106. In the first clock period, this would be 100 . . . 000. Digital VREF/2 is then converted to analog VREF/2 by the DAC 108, which is passed to the comparator for comparison step 104. If the comparator result at the next clock cycle is 1, then the SAR would register 110 . . . 000. After each comparison, the comparator is reset to prepare it for the next comparison.
Steps 104, 106 and 108 are repeated once per clock cycle for N Bits 110, therefore if the conventional successive approximation ADC is N-bit, the elapsed time to convert a signal is N clock periods.
During the second clock period, in the example where the partial digital value of the SAR is 110 . . . 000, VDAC recomputed to be VREF/2+VREF/4,. If the comparator result is high, the SAR will be updated to 111 . . . 000 (if the comparator result is low, the SAR will be updated to 101 . . . 000). In this way, the two most significant bits (MSB) of the digital value of the SAR have been determined in the first two clock cycles. In the (N+1)th clock period, the digital value of the SAR will be outputted and the method 20 will repeated for the first clock cycle and so on, as discussed above.
“There are several problems with the conventional successive approximation ADC. First, since the number of conversion bits is determined sequentially, each bit of resolution requires a conversion operation. As a result, the conversion time tends to become unacceptably long for high-speed and high-resolution applications. Second, the typical ADC of this type employs a switching capacitor as the DAC; these devices tend to exhibit the traits of charge injection during switching, as well as embodying long settling times. Both of these traits tend to interfere with optimum operation of the ADC.”
What is needed, then, is a recursive ADC that combines the cost benefits of a SAR-based architecture with the high speed and high resolution of a non-recursive ADC.